1. Field of the Invention
The invention relates to a method for fabricating contacts, in particular bit line contacts, for an integrated circuit (IC) on a semiconductor wafer, and to a semiconductor component having a contact of this type, in particular for use in a dynamic random access memory (DRAM).
2. Description of the Related Art
Making electrical contact with active areas (AAs), which in the context of the present application is to be understood as meaning those regions of a semiconductor surface in which electrically active structures, such as for example transistors, capacitors or any semiconductor structures which belong to a memory cell of a DRAM, are embedded, represents one of the central problems in the manufacture of modern ICs and in particular DRAMs. Low electrical resistances and small capacitances are indispensable in order to achieve rapid electrical switching operations.
According to the prior art, to make contact with an active area of an integrated circuit on a semiconductor chip, for example with a (metallic) bit line above it, contact structures are formed in an insulator layer of the semiconductor chip and are then filled with a conducting material. The band structure of this conducting material is preferably matched to the band structure of the active area below it, with which contact is to be made. In the case of ICs which are based on silicon, the conducting material used is generally doped polysilicon.
In the processes which have hitherto been customary for making contact with active areas, the contacts are fabricated by means of a multistage method. A homogeneous insulator layer, for example of SiO2 which is deposited using the TEOS process, is applied to the surface of the semiconductor wafer to which control lines, which are generally already enclosed in an insulator layer (e.g. consisting of silicon nitride), such as for example gate lines (gate contacts, GC, e.g. comprising doped polysilicon), have generally already been applied. In a subsequent method step, which comprises a photolithographic patterning operation and a subsequent locally active etching step, this homogeneous insulator layer is provided with what is known as a contact hole in the region of the active area with which contact is to be made. This contact hole is then filled with a conducting material and finally is covered with an extensive (metallic) bit line, resulting in electrically conductive contact between active area and bit line (bit line contact CB).
The contact hole which has been produced in the insulator layer extends as far as the surface of the active area, which generally, for process reasons, has been covered with an insulating native SiO2 layer which is a few nanometers thick. In order, despite this insulator layer, to produce an electrically conductive connection between the active area and a conducting material which is to be introduced into the contact hole during a subsequent process step, various methods are known for eliminating the native oxide layer, the application of which is dependent on the particular conducting material used.
If polysilicon is used as conducting material (polysilicon process), which offers particular advantages on account of the fact that its band structure is close to that of the active area, the native oxide layer has to be removed in a preceding, generally wet-chemical cleaning step. Chemical substances, such as BHF, are used for this purpose and, which in addition to attacking the native oxide layer, often also attack the insulator layer which has been applied to the entire surface or the insulating cladding of the gate lines. This may lead to locally undefined removal of material from the insulator layers, in particular at the edges thereof.
Widening of the contact hole which cannot be accurately controlled and is inevitably associated with the above cleaning step causes particular difficulties in terms of process technology. If the contact hole is additionally spatially delimited by gate lines, material may likewise be removed in an undefined manner from the insulator layers which surround these gate lines. Extensive removal of the material from the surrounding insulator layers may in extreme circumstances even lead to the embedded gate line being uncovered. If the contact hole is filled with polysilicon in the subsequent method step, an electrically conductive connection may be formed between polysilicon/bit line, on the one hand, and gate line, on the other hand, i.e. the associated electronic component is short-circuited.
However, removing too little material during the wet-chemical cleaning step leads to incomplete removal of the native oxide layer. Therefore, during the subsequent filling of the contact hole with polysilicon, there is no electrically conductive contact produced between the active area and the polysilicon. Ultimately, there is no electrical contact produced between the bit line and the active area, and contact is therefore not made with the associated electronic component.
To limit this difficulty in terms of process technology, hitherto the diameter of the contact hole has been selected to be small, in order to maintain a considerable distance from any gate lines which may be present and thereby to minimize the risk of short circuits between gate lines and bit lines. However, such a small diameter of the contact hole leads to further difficulties in terms of process engineering. For example, as the structures become ever smaller, it becomes more difficult to produce sharply delineated structures, on account of the nonlinear nature of the photolithographic process, and on the other hand in the case of small structures the aspect ratio during the subsequent etching step is greatly limited.
Therefore, during the further development of the known polysilicon process, primarily the chemical selectivity of the etching process has been optimized, in order to avoid undesirable removal of material from the insulator layers surrounding the gate lines. However, this requires the use of different materials for the insulation which surrounds the gate lines and the large-area insulator layers.
The German application which bears the reference number 101 19 873.6, which is in the name of the present applicant and has not yet been published, has disclosed an alternative method for fabricating contacts on semiconductor surfaces, which is based on the use of metals as conducting materials for filling the contact holes. In one configuration of the method, the metallic conducting material is introduced into the contact holes by means of the (dual) damascene process.
In an advantageous refinement of this known method, there is no need for wet-chemical removal of the native oxide on the surface of the active areas, since the native oxide is removed using the “self-aligned contacts” (SAC) method by means of reducing silicon formation between metallic conducting material and native oxide. However, the “self-aligned contacts” method is restricted to a small number of metals. Only the metals Mo, W, Ti and Ta are particularly suitable, and hitherto the use of Ti has dominated. If other metals, such as for example Cu, are used as conducting material, in general an etching step is required once again for removal of the native oxide layer, which has all the drawbacks which have been mentioned above.
Moreover, when a metallic conductor material is used, targeted doping of the surface of the active area is necessary in order to produce a metal-semiconductor ohmic contact. This doping with subsequent annealing step requires additional method steps, which entail additional costs.